1. Field of the Invention
This invention relates to an improved method and apparatus for generating critical timing signals. For example, timing signals required in the operation of dynamic random access memories (DRAMs). More particularly it relates to a digital system and method to generate precisely positioned timing signals, independently of system component variations due to manufacturing process variations, or temperature variations, or both, and independently of clock edge location.
2. Description of the Prior Art
There have been a number of systems used in the prior art to generate critical timing signals. For DRAMs, such signals include the leading and trailing edges of a row address strobe, a column address strobe, and a signal to transition from row address to column address. Analogue delay lines, digital delay lines, and programmable cycle delays have been used in the prior art to generate these critical timing edges. While generally satisfactory, each of these prior art approaches has certain limitations and disadvantages. Significantly, previous programmable cycle delays have restricted critical signal edges to clock boundaries or delayed them sufficiently to guarantee they do not arrive too early under best case tolerance and operating conditions, and thus in either case have compromised performance. For example, if the system operation calls for a timing edge only a short interval after the clock edge, with the prior art system the timing signal would be generated at the next clock edge, resulting in the loss of time on the order of a whole clock cycle.